1. Field of the Invention
The invention relates generally to electrostatic discharge (ESD) protection for an integrated circuit (IC), and more particularly, to a self-aligned silicide (SALICIDE) process for improving the ESD protection capability of an integrated circuit.
2. Description of Related Art
During handling of integrated circuits, operators or IC transport equipment generate electrostatic charges due to turboelectric effect. These electrostatic charges may seriously damage the IC.
A metal oxide semiconductor field-effect transistor (MOSFET) IC is most susceptible to electrostatic discharge due to its high input resistance and low breakdown voltage. As a result, an ESD protection device is typically attached to a MOSFET IC where electrostatic discharge occurs most frequently, e.g., at an I/O port, to prevent destruction of a discharge path of the IC.
FIGS. 1A-1G illustrate the conventional process of forming an electrostatic discharge protection device.
As shown in FIG. 1A, the conventional process includes the step of providing a silicon substrate 10 with an internal circuit area 12 and an electrostatic discharge protection area 14. Both areas 12, 14 comprise at least one polysilicon gate electrode 16a and 16b, respectively, and lightly-doped areas 18a and 18b, respectively, formed beside polysilicon gate electrode 16a, 16b, wherein gate electrode 16a and area 18a and gate electrode 16b and area 18b represent source-drain areas of internal circuit area 12 and electrostatic discharge protection area 14, respectively.
Referring to FIGS. 1B and 1C, the conventional process further includes the steps of depositing a silicon dioxide layer 20 on the surface of silicon substrate 10, and etching silicon dioxide layer 20 to form polysilicon gate spacers 22 for internal circuit area 12 and electrostatic discharge protection area 14. Using polysilicon gate spacers 22 as a mask, the conventional process further includes using ion implantation to form heavily-doped areas 21a, 21b in internal circuit area 12 and electrostatic discharge protecting area 14, wherein the source-drain areas form lightly doped drains (N+ areas).
FIGS. 1D and 1E illustrate the process of forming a self-aligned silicide layer. The process comprises the steps of sputtering a titanium layer 24 on the surface of substrate 10 so to chemically react with the Si material of substrate 10 and to form a silicon titanium layer 26. The titanium contacting a nonpolysilicon surface of the device and the titanium contacting the substrate surface but not affected by the chemical reaction, are subsequently removed using a selective etching solution.
Finally, as shown in FIGS. 1F and 1G, the conventional process further includes the steps of depositing a dielectric layer 28 on the entire device and forming contact windows 30 in dielectric layer 28.
In the conventional process for making an electrostatic discharge protection device, the source-drain areas are formed as lightly-doped drain (LDD) structures so to prevent a short channel effect in the internal circuitry. However, these LDD structures increase the short channel effect, which decrease the electrostatic discharge responsiveness of the electronic discharge protection device. Thus, if a large current is supplied in conventional ICs, then the electrostatic discharge protection device must provide a path for rapid discharge.
Further, in the conventional process for making ESD protection devices, the self-aligned silicide step forms a silicide layer on the surface of the gate electrode, improving the conductivity of the polysilicon gate electrode of the internal circuit area and preventing a high resistance in the polysilicon gate electrode. However, the silicide layer also reduces the electrostatic discharge responsiveness of the electrostatic discharge protection device. Thus, the benefits achieved by the silicide layer in the internal circuit is a disadvantage in conventional electrostatic discharge protection devices.
Finally, in the conventional process for making ESD protection devices, the silicide layer remaining on the surfaces of the source-drain areas in the electrostatic discharge protection area must be removed by etching. However, this etching damages the source-drain areas, forming defects therein.